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Device Design and Simulation

SiCED has installed the latest version of the Synopsys 3D device Simulator

Read more!

Device Characterization

End of life tests and the Investigation of the related physical phenomena will be a major topic for future work

Read more!
Wafer

!!! U P D A T E !!!  

  

New VJFET chip available

SiCED has a new VJFET chip type on stock (Ubr > 1200V). The die size is 4.16x4.16mm, a typical Ron at room temperature is <120mΩ. A Spice model for this chip in TO220 is availabe in the VJFET chapter.


New diode chip available

SiCED can offer a Schottky Diode with large area (4.8x4.8mm²), for a blocking voltage of 1200V and a rated current of approximately 50A . More information can be found in the section  Schottky Diode.

!!! UPDATE  !!!

  

Spice Model for SiC VJFET

A revised version of the PSpice Model for the VJFET is available for download in the VJFET-Section. The optimization is mainly related to the convergence in dynamic simulations.


International conference on Silicon Carbide and Related Materials (ICSCRM) 2009

The next ICSCRM will  be held in Nuremberg, Germany. SiCED will be involved in the planning and organization of this event. For details please refer to www.icscrm2009.org.


SiCED prepares for the future - Aixtron G4 platform will serve for next generation SiC epitaxy

SiCED has signed a purchase and development agreement with AIXTRON AG Germany, about their latest generation of planetary reactors, suited for 10x100mm or 6x150mm wafers. Find more details in the epi-section.